In order to improve both performance and integration level of integrated circuits, the feature sizes of devices are scaled down according to Moore's law, which nowadays have reached into the nanometer regime. However, power consumption and current leakage become the most concerned issues along with downscaling in dimensions of the devices. Owing to its capability of suppressing short-channel effect and facilitating proportional downscaling of the devices, the Silicon on Insulator (SOI) architecture has become a preferred structure for deep sub-micrometer or nanometer MOS devices.
Along with the development in SOI technology, Malgorzata Jurcazak, Thomas Skotnicki and M. Paoli have proposed an innovated SOI device—Silicon on Nothing (SON) device structure, in which the channel region is deposed on a cavity, in the article “Silicon-on-Nothing—an Innovative Process for Advanced CMOS” (IEEE TRANSACTIONS ON ELECTRON DEVICES, vol. 47, NO. 11, November 2000).
SON (Silicon on Nothing) is an advanced technology developed by CEA-Leti and STmicroelectronics for manufacturing CMOS at 90 nm or below technical nodes; since SON proposes to form a localized SOI (silicon on insulator) under a channel through a “cavity” architecture, the cavity may indicate an air gap or an oxide filling. As compared to an SOI device, the dielectric constant of the cavity architecture is significantly reduced, which considerably smoothes the two-dimensional electrical field effect of the buried oxide layer, and significantly reduces DIBL; the thickness of the silicon film and the height of the cavity may be controlled to produce an optimized short-channel characteristics and to achieve a rather steep sub-threshold slope; meanwhile, the self-heating effect of SOI devices is alleviated; additionally, it is applicable to use bulk silicon wafers as original wafers instead of expensive SOI wafers. As such, SON is regarded as a preferred architecture for substituting SOI technology.
The most critical issue in manufacturing an SON device is how to manufacture a cavity layer. When the SON architecture was first proposed, it made use of an epitaxial SiGe sacrificial layer process. Later, another article revealed a method for manufacturing an SON device through He ion implantation accompanied with annealing or through H—He ion co-implantation accompanied with annealing. The process of epitaxial SiGe sacrificial layer increases the number of steps for manufacturing the device, and increases complexity of the process as well. However, along with downscaling of feature sizes of devices, the ion implantation processes also encounter problems because of requirement of ultra-shallow junction depth of the devices. In a word, there are still lots of challenges remain in the prior art to be tackled when making use of the current processes for manufacturing ultra-large-scale integrated circuits.
Because the contact resistance between contact vias and source/drain regions will not decrease proportionally to the downscaling of the transistor size, thus reducing the contact resistance at the source/drain regions becomes a critical factor to improve performance of transistors. A metal silicide contact layer is widely used in the deep sub-micrometer or smaller MOS transistors to reduce contact resistance at the source/drain regions. However, in SON devices, how to manufacture a contact layer and how to increase the area of a contact layer still face many challenges.